The 3D Circuit technologies appear as a possible solution for interconnect optimization. For most of the 3D technologies, the 3D-Vias represent a very complex issue because of large pitch requirements and heavy usage of routing constraints. This paper studies the impact of I/O pins partitioning in 3D circuits. Previous works on 3D placement did not focus on the I/Os partitioning and placement. This work presents an algorithm based on the logic proximity of the pins, which is used as weights to a min-cut partitioning. Our method calculates the area of the tiers while placing the I/Os on the boundaries. Initial whitespace and aspect ratio as well as the initial pins orientation and ordering are preserved. We compared to two other methods for pins partitioning. Our experimental results show that our method is efficient since it can balance the I/O pins distribution in the various tiers while leading to improvements in wire length and number of 3D vias.