Analysis and design of algorithms for the manufacturing process of integrated circuits
DOI:
https://doi.org/10.19153/cleiej.26.2.2Keywords:
integrated circuit manufacturing, back-end production, chip placement process, greedy algorithm, genetic algorithm, pick-and-place, integer linear programmingAbstract
The stage of transporting semiconductor chips from the wafer to the support strip is crucial in the integrated circuit manufacturing process. This process can be modeled as a combinatorial optimization problem where the objective is to reduce the total distance the robotic arm must travel to pick up each chip and place it in its corresponding position within the support structure. This problem is of the pick-and-place type and is NPhard. The (approximate) solution proposals of state-of-the-art methods include rulebased approaches, genetic algorithms, and reinforcement learning. In the present work, one of these methods is analyzed, which models the problem as one of binary integer programming and proposes a genetic algorithm. Based on this analysis, we proposed
and evaluated other methods, including a greedy algorithm and a genetic algorithm that improve the state-of-the-art results for test cases usually used in the literature. Additionally, the results obtained from a new ILP model for this problem indicate that the genetic algorithm results are very close to the optimal values.
Downloads
Published
Issue
Section
License
Copyright (c) 2023 Sonia Fleytas, Diego P. Pinto-Roa, Jose Colbes
This work is licensed under a Creative Commons Attribution 4.0 International License.
CLEIej is supported by its home institution, CLEI, and by the contribution of the Latin American and international researchers community, and it does not apply any author charges whatsoever for submitting and publishing. Since its creation in 1998, all contents are made publicly accesibly. The current license being applied is a (CC)-BY license (effective October 2015; between 2011 and 2015 a (CC)-BY-NC license was used).